1. Field of the Invention
The present invention relates to a boosting circuit for generating positive/negative high voltages that differ in voltage level in accordance with an operation mode, contained in a non-volatile semiconductor storage device.
2. Description of the Related Art
In a non-volatile semiconductor storage device such as a flash EEPROM (electrically erasable programmable read-only memory), it is required that a positive high voltage higher than a supply voltage and a negative high voltage lower than a ground potential, which are different in voltage level and current ability, are applied to a memory cell array transistor in accordance with read, erasure, and write modes. Recently, due to the demand for the miniaturization of a system, the decrease in a supply voltage, the power consumption, and the like, it is desired that a boosting circuit for generating a high voltage be contained in a non-volatile semiconductor storage device, and a boosting efficiency of the boosting circuit is enhanced.
Furthermore, in order to generate positive/negative high voltages that are different in voltage level and current ability in one boosting circuit, plural-stage charge pump circuits connected in series with each other are provided, and the number of the stages is switched.
FIG. 9 is a circuit diagram showing an exemplary configuration of a negative boosting circuit for generating negative high voltages different in voltage level as a conventional boosting circuit. In FIG. 9, reference numerals 11, 12, 13, and 14 denote charge pump circuits (PUMP1, PUMP2, PUMP3, PUMP4) of a threshold canceling type. Assuming that the high level of clock signals CLK3 and CLK2 is a supply voltage VDD, and the low level thereof is a ground potential VSS (=0 V), each charge pump circuit boosts an input voltage to a negative side by −VDD and outputs it. Other clock signals CLK1 and CLK4 have the same amplitude as that of the clock signals CLK3 and CLK2. The input voltage to the charge pump circuit 11 is 0 V, so that the output voltage thereof is −VDD, and the output voltage of the charge pump circuit 12 that receives the voltage −VDD is −2VDD. Thus, negative high voltages in a range of 0 V to −2VDD are generated by the 2-stage charge pump circuits 11 and 12. Furthermore, an input voltage is boosted to a negative side by −2VDD by the 2-stage charge pump circuits 13 and 14. The detail of the charge pump circuits 11 to 14 of a threshold canceling type will be described later.
Reference numeral 60 denotes a stage-number switching circuit for switching the number of stages of charge pump circuits. In the case where a stage-number switching control signal SWHON to be input to the stage-number switching circuit 60 is at a logic low level (i.e., the stage-number switching circuit 60 is deactivated), a level shift circuit LS1 turns off an N-channel MOS transistor Tn1 and turns on an N-channel MOS transistor Tn2. Because of this, the 2-stage charge pump circuits 11 and 12 and the 2-stage charge pump circuits 13 and 14 are connected in parallel with each other. As a result, the output voltage −2VDD of the 2-stage charge pump circuits 11 and 12 causes a first negative voltage VNN1 (=−2VDD) to be output as a negative voltage VNN through a P-channel MOS transistor Tp1 connected as a diode for preventing a reverse flow. Furthermore, the output voltage −VDD of the 2-stage charge pump circuits 13 and 14 causes a first negative voltage VNN1 (=−2VDD) to be output as a negative voltage VNN through a P-channel MOS transistor Tp2 connected as a diode for preventing a reverse flow (Route (1)).
On the other hand, in the case where the stage-number switching control signal SWHON is at a logic high level i.e., the stage-number switching circuit 60 is activated), the level shift circuit LS1 turns on an N-channel MOS transistor Tn1, and turns off an N-channel MOS transistor Tn2. Because of this, the 2-stage charge-pump circuits 11 and 12 and the 2-stage charge-pump circuits 13 and 14 are connected in series with each other. As a result, the output voltage −2VDD of the 2-stage charge pump circuits 11 and 12 is supplied to the charge pump circuit 13 through a P-channel MOS transistor Tp3 connected as a diode for rectifying a voltage and an N-channel MOS transistor Tn1, and boosted to −4VDD by the 2-stage charge pump circuits 13 and 14. As a result, the input voltage −4DD causes a second negative voltage VNN2 (=−4VDD) to be output as a negative voltage VNN through a P-channel MOS transistor Tp2 connected as a diode for preventing a reverse flow (Route (2)). In this case, the P-channel MOS transistor Tp1 connected as a diode for preventing a reverse flow is in a reverse bias state to be turned off.
Thus, the stage-number switching circuit 60 generates two negative high voltages different in voltage level in the same negative boosting circuit. Cp1 denotes a smoothing capacitor for an output.
Conventionally, in order to suppress a supply voltage VEE of the level shift circuit LS1 from being fluctuated due to a pumping operation in the stage-number switching circuit 60, the P-channel MOS transistor Tp3 connected as a diode for rectifying a supply voltage and a smoothing capacitor Cp2 are provided.
Next, the configuration and operation of the 2-stage charge pump circuits 11 and 12 shown in FIG. 9 will be described with reference to FIGS. 10 and 11.
FIG. 10 shows a circuit diagram showing an internal configuration of the 2-stage charge pump circuits 11 and 12, and FIG. 11 is a timing chart of four clock signals CLK1, CLK2, CLK3, and CLK4 supplied to the 2-stage charge pump circuits 11 and 12.
In FIG. 10, P-channel MOS transistors (hereinafter, referred to as “charge transfer transistors”) Tp5 and Tp7 are connected between the ground potential and the output VOUT so that current channels thereof are connected in series with each other. One electrode of a capacitor Cp4 is connected to a connection node N5 of the charge transfer transistor Tp5 and one electrode of a capacitor Cp6 is connected to an output node N7 of the charge transfer transistor Tp7. The other electrode of the capacitor Cp4 is supplied with the clock signal CLK3 having an amplitude of a supply voltage VDD, and the other electrode of the capacitor Cp6 is supplied with the clock signal CLK2 having an amplitude of the supply voltage VDD. One electrode of the capacitor Cp3 is connected to a gate of the charge transfer transistor Tp5, and one electrode of the capacitor Cp5 is connected to a gate of the charge transfer transistor Tp7. The other electrode of the capacitor Cp3 is supplied with the clock signal CLK1 having an amplitude of the supply voltage VDD, and the other electrode of the capacitor Cp5 is supplied with a clock signal CLK4 having an amplitude of the supply voltage VDD.
Furthermore, the current channels of the threshold canceling P-channel MOS transistors (hereinafter, referred to as “threshold canceling transistors”) Tp4 and Tp6 are connected between the gate and the drain of the charge transfer transistors Tp5 and Tp7, respectively. Each gate of the threshold canceling transistors Tp4 and Tp6 is connected to each source (nodes N5 and N7) of the charge transfer transistors Tp5 and Tp7. The threshold canceling transistors Tp4 and Tp6 are provided so as to cancel (compensate for) threshold voltages of the charge transfer transistors Tp5 and Tp7 that are operated as diodes.
Next, the boosting operation of the 2-stage charge pump circuits 11 and 12 thus configured will be described with reference to a timing chart in FIG. 11.
First, at a time t1 in FIG. 11, the clock signal CLK4 rises from 0 V to VDD. As a result, the voltage level of the node N6 is increased due to the coupling with the capacitor Cp5. Furthermore, the charge transfer transistor Tp7 is turned off, and the node N7 is put in a floating state.
Next, at a time t2, the clock signal CLK2 falls from VDD to 0 V As a result, the voltage level V7 of the node N7 is decreased due to the coupling with the capacitor Cp6. The threshold canceling transistor Tp6 is turned on, and the voltage level of the node N5 becomes the same as that of the node N6.
Next, at a time t3, the clock signal CLK3 rises from 0 V to VDD. As a result, the voltage level V5 of the node N5 is increased due to the coupling with the capacitor Cp4. Furthermore, the threshold canceling transistor Tp4 is turned off, and the node N4 is put in a floating state.
Next, at a time t4, the clock signal CLK1 falls from VDD to 0 V As a result, the voltage level of the node N4 is decreased due to the coupling with the capacitor Cp3. Furthermore, the charge transfer transistor Tp5 is turned on, and a current flows from the node N5 to a ground potential, whereby the voltage level V5 of the node N5 is decreased.
Next, at a time t5, the clock signal CLK1 rises from 0 V to VDD. As a result, the voltage level of the node N4 is increased due to the coupling with the capacitor Cp3. Furthermore, the charge transfer transistor Tp5 is turned on, and the node N5 is put in a floating state.
Next, at a time t6, the clock signal CLK3 falls from VDD to 0 V As a result, the voltage level V5 of the node N5 decreases due to the coupling with the capacitor Cp4. Furthermore, the threshold canceling transistor Tp4 is turned on, and the node N4 reaches a ground potential (0 V).
Then, at a time t7, the clock signal CLK2 rises from 0 V to VDD. Because of this, the voltage level V7 of the node N7 is increased (V5<V7) due to the coupling with the capacitor Cp6. Furthermore, the threshold canceling transistor Tp6 is turned off, and the node N6 is put in a floating state.
Next, at a time t8, the clock signal CLK4 falls from VDD to 0 V As a result, the voltage level of the node N6 is decreased due to the coupling with the capacitor Cp5. Furthermore, the charge transfer transistor Tp7 is turned on, and a current flows from the node N7 to the node N5 because of the relationship V5<V7 at the time t7, whereby the voltage level V7 of the node N7 is decreased.
Finally, a current flows to a ground potential through the charge transfer transistor Tp5, whereby the voltage level of the node N5 is decreased to −VDD. Furthermore, a current flows to the node N5 through the charge transfer transistor Tp7, whereby the voltage level of the node N7 is decreased to −2VDD. As a result, a negative high voltage of −2VDD is generated as an output voltage VOUT.
The principle by which a negative high voltage −2VDD is obtained from the 2-stage charge pump circuits 11 and 12 is as described above.
Conventionally, as shown in FIG. 9, in order to suppress the supply voltage VEE of the level shift circuit LS1 from being fluctuated due to a pumping operation, the P-channel MOS transistor Tp3 connected as a diode for rectifying the supply voltage VEE and the smoothing capacitor Cp2 are provided in the stage-number switching circuit 60.
Therefore, in the case where a second negative voltage VNN2 is generated in the Route (2) in which the 2-stage charge pump circuits 11 and 12 are connected in series with the 2-stage charge pump circuits 13 and 14, the boosting current ability in an output terminal is decreased by a threshold voltage Vth of the P-channel MOS transistor Tp3 connected as a diode in the stage-number switching circuit 60, and a boosting efficiency is decreased. In order to suppress the decrease in a boosting efficiency, it is required that the size of the P-channel MOS transistor Tp3 is increased, and the threshold voltage Vth is decreased. Because of this, a chip area is increased.
Furthermore, by using the smoothing capacitor Cp2, the time required for reaching the second negative voltage VNN2 is prolonged due to a time constant composed of an ON-resistance of the P-channel MOS transistor Tp3 and the capacitance of the smoothing capacitor Cp2.